1. Field of the Invention
The present invention relates to an instruction processing apparatus for sequentially executing instructions, and more specifically to an instruction processing apparatus for sequentially performing operations of referring to and updating resources accessible by a program, that is, a storage area of memory, the contents of a register, etc., in the instruction execution order.
2. Description of the Related Art
In the information processing apparatus, various technologies have been used to quickly perform a process on an instruction. A first technology is a pipeline process. By setting a number of smaller stages in a process, that is, setting a pipeline process, a higher-speed machine cycle can be realized. As a result, a system referred to as a super-pipeline, a super-scalar system in which a plurality of pipelines are mounted, etc. have been put to a practical use as pipeline process technologies.
As a second technology, an instruction is executed and controlled using a stack awaiting a process to be performed and referred to as a reservation station instead of the control of the execution of an instruction by a pipeline. In the system using a reservation station, unlike the pipeline system, the number of entries of a stack can be selected independent of the number of the process steps in a machine cycle unit, and high parallelism can be attained by setting a larger number of entries.
An out-of-order system can be used as a third technology for higher performance. An out-of-order system performs a process in an order different from an instruction order directed by a program, that is, executes instructions from any one, for example, whose input data have been prepared. That is, in the out-of-order system, an entry which can be processed in a stack is selected, and a process corresponding to the entry can be performed in an order different from an instruction order directed by a program.
Although an arbitrary instruction execution order can be set in the out-of-order system, the instructions have to be executed such that the resources accessible by a program, that is, the storage area of memory, the contents of a register, etc. can be referred to or updated according to the program execution order.
A register renaming technology has been suggested as a technology of guaranteeing that the contents of a register can be referred to and updated in the program execution order. In the conventional register renaming process, physical registers larger in number than the logical registers specified by the architecture are prepared, and the logical registers are all mapped corresponding to the physical registers, and then referred to and updated. The physical registers are larger in number than the logical registers because the contents of the physical registers corresponding to the logical registers have to be stored in case a pipeline may be cleared for any reason.
Thus, by increasing the number of entries of a stack in the reservation station system for execution at a higher speed than the pipeline system, the performance of a process per unit clock can be improved, but the amount of hardware also increases. In addition, since the number of function execution units are limited, an entry corresponding a process to be performed has to be selected from among a number of entries to execute an instruction. As a result, with an increasing amount of hardware, the machine cycle is reduced, thereby hardly improving the entire performance.
In the out-of-order system, it is necessary to have a system of performing a process for observing an operation of updating programmable resources, which are maintained regardless of an execution order of an operation process, etc., such as a storage area of memory, the contents of a register, etc. as if the process were performed in an instruction execution order. The system can be, for example, the above mentioned register renaming process. To attain this, the amount of hardware increases, the hardware becomes more complicated, and an enhanced machine cycle can hardly be realized.
Furthermore, to prevent a machine cycle from reducting and a amount of hardware from increasing, the pipeline system is to be combined with the reservation station system so that a process can be divided into a plurality of stages each having a stack. In this method, a stage has to be completed before starting the next stage, and it is difficult to pass control between the stages with the instruction execution order of a program ignored, thereby failing to overcome the limit of the pipeline process system.
It is therefore one object of the present invention to provide an apparatus that will be capable of executing an instruction at a high speed by independently providing an instruction reservation station storing data, etc. corresponding to the type of an instruction for one instruction, and one or more function reservation stations corresponding to the function relating to the execution of the instruction.
According to the present invention, an apparatus for executing instructions includes: an instruction reservation station unit for storing data for each type of instruction corresponding to an individual instruction, and integrally controlling the update of resources relating to the completion of the execution of the instruction; and one or more function reservation station units for storing data corresponding to the function relating to the execution of the instruction, and controlling the execution of the function according to the integral control performed by the instruction reservation station unit.
According to the present invention, an entry of the instruction reservation station unit corresponding to each instruction, and an entry of one or more function reservation station units corresponding to the function relating to the execution of an instruction are independently generated. Therefore, instructions can be executed from any executable instruction, and the resources can be updated in an instruction execution order, thereby greatly improving the parallelism of the processes, and successfully improving the performance of the instruction processing apparatus.